『FPGAボードで学ぶVerilog HDL』 (12) 第4章「180秒タイマを作る」3(後編)

「『FPGAボードで学ぶVerilog HDL』 (12) 第4章「180秒タイマを作る」3(前編)」の続き

Verilog HDL 記述の書き換え(続き)



oe_gen.v

module oe_gen(
clk,
OE_DIGIT
);

input clk;
output [1:0] OE_DIGIT;

reg [19:0] OEN_counter;

always @(posedge clk)
begin
OEN_counter <= OEN_counter + 1;
end

//assign OE_DIGIT = OEN_counter[19:18];
assign OE_DIGIT = OEN_counter[17:16];

endmodule


seg7enc.v

module seg7enc(
hex4_in,
seg7_out
);

input [3:0] hex4_in;
output reg [7:0] seg7_out;

always @*
begin
case (hex4_in)
4'b0000 : seg7_out <= 8'b00111111;
4'b0001 : seg7_out <= 8'b00000110;
4'b0010 : seg7_out <= 8'b01011011;
4'b0011 : seg7_out <= 8'b01001111;
4'b0100 : seg7_out <= 8'b01100110;
4'b0101 : seg7_out <= 8'b01101101;
4'b0110 : seg7_out <= 8'b01111101;
4'b0111 : seg7_out <= 8'b00100111;
4'b1000 : seg7_out <= 8'b01111111;
4'b1001 : seg7_out <= 8'b01101111;
default : seg7_out <= 8'b01000000;
endcase
end

endmodule


seg7out.v

module seg7out(
OE_DIGIT,
TIM_1,
TIM_2,
TIM_3,
SEG_O
);

input [1:0] OE_DIGIT;
input [3:0] TIM_1, TIM_2, TIM_3;
output [7:0] SEG_O;

reg [3:0] data;
wire [7:0] seg7out;

//always @(OE_DIGIT)
always @*
begin
case (OE_DIGIT)
2'b00 : data <= TIM_1;
2'b01 : data <= TIM_2;
2'b10 : data <= TIM_3;
default : data <= 4'b1111;
endcase
end

seg7enc I_seg7enc(
.hex4_in(data),
.seg7_out(seg7out)
);

assign SEG_O = ~seg7out;

endmodule


seg7en.v

module seg7en(
OE_DIGIT,
SEGEN_O
);

input [1:0] OE_DIGIT;
output [3:0] SEGEN_O;

reg [3:0] SEGEN;

always @(OE_DIGIT)
begin
case (OE_DIGIT)
2'b00 : SEGEN <= 4'b0001;
2'b01 : SEGEN <= 4'b0010;
2'b10 : SEGEN <= 4'b0100;
default : SEGEN <= 4'b1000;
endcase
end

assign SEGEN_O = ~SEGEN;

endmodule


トップモジュール TIM180.v

module TIM180(
CLK_I,
SW_START_I,
SW_RESET_I,

SEG_O,

DPOEN_O,

LED1_O,
LED2_O,
LED3_O,
LED4_O
);

input CLK_I;
input SW_START_I;
input SW_RESET_I;

output [7:0] SEG_O;

output [3:0] DPOEN_O;

output LED1_O;
output LED2_O;
output LED3_O;
output LED4_O;

wire [31:0] sec1_counter;
wire [7:0] TIME;
wire [3:0] TIM_3, TIM_2, TIM_1;
wire TIM_ZERO;
wire [7:0] remainder3;
wire [3:0] remainder2;
wire pulse_1sec;
wire [1:0] OE_DIGIT;
wire TIM_START, TIMEOUT;

fsm I_fsm(
.clk(CLK_I),
.reset(SW_RESET_I),
.start_i(SW_START_I),
.tim_zero(TIM_ZERO),
.pulse_1sec(pulse_1sec),
.start_o(TIM_START),
.timeout(TIMEOUT)
);

assign TIM_ZERO = TIME == 0;

pulse1sec I_pulse1sec(
.clk(CLK_I),
.reset(SW_RESET_I),
.start(TIM_START),
.sec1(pulse_1sec),
.sec1_counter(sec1_counter)
);

down_time I_down_time(
.clk(CLK_I),
.reset(SW_RESET_I),
.enable(pulse_1sec),
.out(TIME)
);

bin2dec3 I_bin2dec3(
.TIME(TIME),
.timeout(TIMEOUT),
.out(TIM_3),
.remainder(remainder3)
);

bin2dec2 I_bin2dec2(
.TIME(remainder3),
.timeout(TIMEOUT),
.out(TIM_2),
.remainder(remainder2)
);

assign TIM_1 = TIMEOUT ? 4'b1111 : remainder2;

oe_gen I_oe_gen(
.clk(CLK_I),
.OE_DIGIT(OE_DIGIT)
);

seg7out I_seg7out(
.OE_DIGIT(OE_DIGIT),
.TIM_1(TIM_1),
.TIM_2(TIM_2),
.TIM_3(TIM_3),
.SEG_O(SEG_O)
);

seg7en I_seg7en(
.OE_DIGIT(OE_DIGIT),
.SEGEN_O(DPOEN_O)
);

assign LED1_O = (TIMEOUT == 1'b0) ? sec1_counter[21] : sec1_counter[24];
assign LED2_O = (TIMEOUT == 1'b0) ? sec1_counter[22] : sec1_counter[24];
assign LED3_O = (TIMEOUT == 1'b0) ? sec1_counter[23] : sec1_counter[24];
assign LED4_O = (TIMEOUT == 1'b0) ? sec1_counter[24] : sec1_counter[24];

endmodule


制約ファイル
NET "CLK_I" LOC = "P63" ;

NET "LED1_O" LOC = "P17" ;
NET "LED2_O" LOC = "P18" ;
NET "LED3_O" LOC = "P22" ;
NET "LED4_O" LOC = "P23" ;

NET "SW_RESET_I" LOC = "P30" ;
NET "SW_START_I" LOC = "P27" ;

NET "DPOEN_O<0>" LOC = "P86";
NET "DPOEN_O<1>" LOC = "P85";
NET "DPOEN_O<2>" LOC = "P3";
NET "DPOEN_O<3>" LOC = "P2";

NET "SEG_O<0>" LOC = "P94";
NET "SEG_O<1>" LOC = "P92";
NET "SEG_O<2>" LOC = "P98";
NET "SEG_O<3>" LOC = "P71";
NET "SEG_O<4>" LOC = "P70";
NET "SEG_O<5>" LOC = "P90";
NET "SEG_O<6>" LOC = "P91";
NET "SEG_O<7>" LOC = "P95";


動作確認


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途中
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まとめ


180秒タイマを秒数ではなく「分」と「秒」で表示するよう書き換えてみた。

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